As shown in FIG. 1, the conventional word line driving circuit comprises: a NAND gate 1 including a decoder; and inverter 2; and N-MOS transistors 3, 4, 7, the components being so arranged as to drive a word line 8 which is connected to a node N4.
Meanwhile, the word line 8 is connected to several or tens of thousands of memory cells 100-100n, and the function of the word line 8 is to drive the transistors assigned to the memory cells.
FIG. 2 is a timing chart showing the operations of the circuit of FIG. 1, and the operations of the circuit of FIG. 1 will be described referring to FIG. 2.
A plurality of address input signals Axl-Axn of FIG. 1 are in a low state, i.e., in a non-activated state, a node N1 will have a high level, and nodes N2-N4 will have a low level as shown in FIG. 2, so that the word line 8 should be in a low state, i.e., in a turned-off state. Then, if the plurality of the address signals Axl-Axn are all shifted to a high level to start an operation, then the output of the NAND gate 1 will have a low level, an N-MOS transistor 7 will be turned off by the node N1 of a low state, the node N2 will be shifted to a high level by the node N2, and an N-MOS transistor 3 will be turned on by a power source voltage VDD, thereby ultimately shifting the node N3.
Meanwhile, the supplying time for an input signal I1 is variable depending on the circumstance, and an input signal as high as VDD+.DELTA.V is supplied to the DRAM in order to pull up the voltage of the word line above the power source voltage VDD.
Thus if the input signal I1 is supplied, then as shown by the dotted lines in FIG. 1, the voltage of the node N3 is boosted above the power source voltage VDD because of the parasitic capacitances G1, G2 (these are produced in a parasitic manner owing to the intrinsic characteristics of MOS process).
Meanwhile, no current path from the node N3 to the node N2 is formed because of the voltage of the node N2 and the voltage VDD of the gate of the N-MOS transistor 3 so as for the boosted voltage of the node N3 to be maintained, and consequently, an input signal having a voltage higher than the voltage VDD is transmitted through an N-MOS transistor 4 to the word line 8.
However, the word line is connected to a large number of cells, and therefore, in the technical constitution of the conventional circuit, there is a severe difference of operational characteristics due to the time delay between the input side of the word line and the end of the word line. Further, the N-MOS transistor 3 is required for supplying a high voltage to the word line, and the N-MOS transistors 3,4 have to have a large size because the N-MOS transistor 4 receives a high pressure when transferring large amounts of current.
Further, the inputs I1 are commonly used for a large number of the word lines at a time, and therefore, a high load is imposed.
Further, a high voltage is required in driving all the word lines, and therefore, a great difficulty is encountered in designing the voltage amplifying circuit.